Mike led the architectural definition and complete engineering development of TIís first OC-48 (2.488Gb/s) compliant SERDES for integration in ASICs. Key transmitter generated jitter specifications are 0.01UI RMS and 0.1UI p-p. for OC48 SONET compliance.

 

Mike led the international debug of the prototype silicon through to customer acceptance.

 

 

HSZ Consulting Ltd

Micro-electronic specialists in mixed-signal design & high speed communications

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130nm OC48 (2.488Gb/s) SONET SERDES.