Mike instigated, architecturally defined and led the technical development of this first-generation ‘clock-cleaning’ PLL in 130nm CMOS. A clock cleaner PLL was key to enabling a new class of SERDES application with relatively high levels of reference clock jitter. Mike led the development from the initial feasibility studies through to customer acceptance.

 

 

HSZ Consulting Ltd

Micro-electronic specialists in mixed-signal design & high speed communications

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130nm LC-tank PLL