Mike led the architectural definition and engineering development of TI’s 65nm 12.5Gbps digital SERDES. This new SERDES architecture digitises the incoming data at 12.5Gbps and performs all equalization and clock recovery functions digitally. Mike was the technical leader for this publicly announced TI/SUN Microsystems collaboration and provided hands-on technical leadership for an international team during the mixed-signal device debug and characterization phases. Mike also led the definition and  development of the second design iteration


Andre designed the Backplane Ethernet support functions external to the SERDES that are required for 802.3ap compliance. They are : 10GBASE-R forward error correction  Backplane auto-negotiation, and Backplane PMD control function (transmit equalizer training).

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65nm 12.5Gbps SERDES