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Micro-electronic specialists in mixed-signal design & high speed communications

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Mike Harwood

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Patents and Papers (Mike)

 

 A 225mW 28Gb/s SerDes in 40nm CMOS With 13dB of Analog Equalization for 100GBASE-LR4 and Optical Transport Lane 4.4 Applications

Mike Harwood, Steffen Nielsen, Andre Szczepanek, Richard Allred, Sean Batty, Mike Case, Simon Forey, Karthik Gopalakrishnan, Larry Kan, Bob Killips, Parmanand Mishra, Rohit Pande, Hamid Rategh, Alan Ren, Jeff Sanders, Albrecht Schoy, Richard Ward, Martin Wetterhorn, Norman Yeung.

Solid-State Circuits Conference, 2012. ISSCC 2012. Digest of Technical Papers

Volume 55: 19-23 Feb 2012, Page(s) 326-7

ISSN 0193-6530

Foil set for this paper as presented at ISSCC2012

 Considerations for CMOS PHY design, Harwood M., EEtimes Analog & Mixed-Signal Applications Conference July 21-22 1997.

 A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery
Harwood, M.; Warke, N.; Simpson, R.; Leslie, T.; Amerasekera, A.; Batty, S.; Colman, D.; Carr, E.; Gopinathan, V.; Hubbins, S.; Hunt, P.; Joy, A.; Khandelwal, P.; Killips, B.; Krause, T.; Lytollis, S.; Pickering, A.; Saxton, M.; Sebastio, D.; Swanson, G.; Szczepanek, A.; Ward, T.; Williams, J.; Williams, R.; Willwerth, T.;
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
11-15 Feb. 2007 Page(s):436 - 591
Digital Object Identifier 10.1109/ISSCC.2007.373481

Foil set for this paper as presented at ISSCC2007