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Mike Harwood

After graduating with an upper 2nd class  honours degree in Physics from Trinity College, Oxford, in 1988, I joined Plessey Research where I spent two years developing mixed-signal, CMOS electronic read-out circuitry for large thermal-imaging arrays.

In 1990, I moved to Texas Instruments where I designed analogue and mixed-signal CMOS integrated circuits for a range of automotive, consumer, networking and data communication applications. These have included TI's CMOS Token-Ring PHY and ThunderLAN (TM) 10/100 Ethernet product family.

From 2000-2009, I primarily led high-speed SerDes and low-jitter PLL developments using advanced CMOS processes. I led TI's 12.5Gb/s SerDes development in 65nm CMOS and was elected a 'Distinguished Member of Technical Staff' within TI's UK SerDes development group.

In 2010 co-founded, set-up and ran Inphi’s UK Design Centre, recruiting eleven engineers whom I directly managed. I either led, or jointly led, the development of seven significant 100Gb/s, CMOS gearbox/CDR products that are now successfully in volume production. In addition, during this time, five SerDes IPs were developed for both external sale and internal company use.

I have both directly managed and technically directed trans-Atlantic design, verification and lab debug teams based in California. I am an accomplished presenter at major conferences, including two presentations (first named author) at ISSCC.

· ‪A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery' at ISSCC 2007.‬

· A 225mW 28Gb/s SerDes in 40nm CMOS With 13dB of Analog Equalization for 100GBASE-LR4 and Optical Transport Lane 4.4 Applications' at ISSCC 2012,‬

‬I have been awarded twenty patents, with two patents pending.

 

 

 

Patents and Papers

Technical Ladder Awards

Analogue Consultant

Phone: +44-7761-530963

Mike holding a 300mm Wafer of 65nm 12.5Gb/s SERDES